Phase comparator and synchronizing signal extracting device

ABSTRACT

While generating a correction pulse (E) based on a clock signal (Xck 1 ) input into one input terminal ( 6 ), a frequency and a phase of a differentiated pulse train (Data_Dif) input into the other input terminal ( 5 ) are compared with a frequency and a phase of the clock signal input into the one input terminal, then a leading phase instructing pulse (U 4 ) and an incomplete lagging phase instructing pulse (D 4   a ) are generated based on this compared result, then false pulses contained in the incomplete lagging phase instructing pulse (d 4   a ) are removed by using the correction pulse (E) when the differentiated pulse train (Data_Dif) input into the other input terminal is in the tooth missing state, and then the precise leading phase instructing pulse (U 4 ) and the precise lagging phase instructing pulse (D 4 ) are output from two output terminals ( 7, 8 ).

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a phase comparator employed inthe data communication system, etc. and a synchronizing signalextracting device using the same and, more particularly, a phasecomparator which can be synchronized with not only the continuousrepetitive pulse but also the discontinuous data pulse with missingpulses since the omission of pulses is caused like the tooth missing anda synchronizing signal extracting device using the same.

[0003] 2. Description of the Related Art

[0004] In the data communication, the data pulse train being sent mustbe interpreted without error to decode the original signal precisely.For this purpose, the synchronizing signal must be detected from thedata pulse train being sent, and then the original signal must bedecoded by using this synchronizing signal. In order to detect thesynchronizing signal, the frequency and the phase must be caused tocoincide with those of the received pulse train. In the prior art, thephase locked loop (referred to as a “PLL” hereinafter) circuit shown inFIG. 1 is normally employed as such detecting means.

[0005] A PLL circuit 150 shown in FIG. 1 comprises the phase comparator151 having a comparing function for comparing a phase of the input pulsewith a phase of the clock signal to output a voltage signal inaccordance with the compared result and a frequency discriminatingfunction, etc., as occasion demands, the low-frequency filter/amplifier152 for extracting a low-frequency component by removing ahigh-frequency component in the voltage signal output from the phasecomparator 151, and the voltage-controlled oscillator 153 foroscillating at a frequency, that responds to the voltage signalcontaining only the low-frequency component being output from thelow-frequency filter/amplifier 152, to generate the clock signal. Inthis PLL circuit 150, when the phase of the clock signal being outputfrom the voltage-controlled oscillator 153 lags behind the phase of theinput pulse, the phase comparator 151 detects this lag and alsoincreases the voltage signal in accordance with this detected result toincrease the frequency of the clock signal being output from thevoltage-controlled oscillator 153 and to advance the phase of the clocksignal. In contrast, when the phase of the clock signal being outputfrom the voltage-controlled oscillator 153 goes ahead of the phase ofthe input pulse, the phase comparator 151 detects this lead and alsodecreases the voltage signal in accordance with this detected result tolower the frequency of the clock signal being output from thevoltage-controlled oscillator 153 and to delay the phase of the clocksignal.

[0006] When the continuously repetitive pulse is input, this PLL circuit150 can relatively easily cause to coincide the phase of the clocksignal being output from the voltage-controlled oscillator 153 with thephase of the input pulse. Therefore, this PLL circuit 150 is extensivelyemployed in the frequency synthesizer, etc.

[0007] However, according to the phase comparator 151 constituting suchPLL circuit 150, the special regard must be paid to the discontinuouspulse train with missing pulses like the tooth missing caused in thedata communication when the pulse train is modulated by the data.Therefore, such PLL circuit 150 cannot attain the sufficient functionand the sufficient performance as the PLL circuit.

[0008] For this reason, in the prior art, as shown in FIG. 2, the phasecomparator 159 was developed (Dan H. Wolaver. Phase Locked Loop CircuitDesign, p.202, Prentice Hall. ISEN 0-13-662743-9) as the phasecomparator that can be applied to such discontinuous pulse train withmissing pulses. This phase comparator 159 comprises two D flip-flopcircuits 154, 155, one inverter circuit 156, and two exclusive-ORcircuits 157, 158, and is able to directly execute the phase comparisonof the discontinuous pulse train, e.g., the NRZ (Non Return toZero)-modulated pulse.

[0009] Also, as shown in FIG. 3, the phase comparator 168 was alsodeveloped (Dan H. Wolaver, Phase Locked Loop Circuit Design, p.221,Prentice Hall, ISBN 0-13-662743-9). This phase comparator 168 comprisestwo D flip-flop circuits 160, 161, two exclusive-OR circuits 162, 163,and four resistors 164, 165, 166, 167, and is able to execute the phasecomparison of the RZ(Return to Zero)-modulated pulse which can beobtained by previously differentiating the NRZ-modulated pulse.

[0010]FIG. 4 shows an outline of the PLL circuit 191 that employs thephase comparator 171 like the phase comparator 159 as the phasecomparator 151, and the charge pump unit 172 as the low-frequencyfilter/amplifier 152. In this case, since the phase comparator 168 hasthe output waveform and the operation almost identical to those of thephase comparator 159, explanation of the PLL circuit employing thisphase comparator 168 will be omitted herein.

[0011] The phase comparator 191 shown in FIG. 4 comprises the phasecomparator 171 for comparing the frequency and the phase of thediscontinuous pulse train Data input into the input terminal 169 withthose of the clock signal Xck1 input into the input terminal 170 andalso generating pulses W, X in accordance with this compared result; thecharge pump unit 172 for increasing the voltage value of the voltagesignal by executing the charging operation when the pulse W is outputfrom this phase comparator 171 and also decreasing the voltage value ofthe voltage signal by executing the discharging operation when the pulseX is output from this phase comparator 171; and the voltage-controlledoscillator 173 for increasing the oscillating frequency as the voltagevalue of the voltage signal being output from this charge pump unit 172is increased higher and also decreasing the oscillating frequency as thevoltage value of the voltage signal being output from this charge pumpunit 172 is decreased lower so as to generate the clock pulse Xck1. Thisphase comparator 191 controls the oscillating frequency of thevoltage-controlled oscillator 173 such that the minimum pulse width ofthe discontinuous input pulse train Data can coincide with therepetitive period of the clock signal Xck1, and generates the clocksignal Xck1 whose frequency is twice the maximum repetitive frequency ofthe discontinuous pulse train Data.

[0012] The phase comparator 171 comprises the D flip-flop circuit 174for acquiring the pulse train Data input into the data input terminal Dwhen the clock signal Xck1 input into the input terminal 170 rises andthen outputting this pulse train Data from the output terminal Q whileholding such pulse train Data; the inverter circuit 175 for invertingthe clock signal Xck1 input into the input terminal the D flip-flopcircuit 176 for acquiring the pulse train Data output from the outputterminal Q of the D flip-flop circuit 174 from the data input terminal pwhen the inverted signal of the clock signal Xck1 output from thisinverter circuit 175 rises and then outputting this pulse train Datafrom the output terminal Q while holding such pulse train Data; theexclusive-OR circuit 177 for calculating the exclusive-OR between thediscontinuous pulse train Data input into the input terminal 169 and thepulse train Data output from the D flip-flop circuit 174 to generate thepulse W; and the exclusive-OR circuit 178 for calculating theexclusive-OR between the pulse train Data output from the D flip-flopcircuit 174 and the pulse train Data output from the delayed flip-flopcircuit 176 to generate the pulse X.

[0013] Then, as shown in (b) of FIG. 5, when the clock signal Xck1 inputinto the input terminal 170 rises, the D flip-flop circuit 174 is causedto acquire the pulse train Data, shown in (a) of FIG. 5, that is inputinto the input terminal 169 and to hold this pulse train Data. When theclock signal Xck1 input into the input terminal 170 falls and theinverted signal of the clock signal Xck1 output from the invertercircuit 175 rises, the D flip-flop circuit 176 is caused to acquire thepulse train Data that is output from the D flip-flop circuit 174 and tohold this pulse train Data. Also, in parallel with the above operations,the exclusive-OR between the pulse train Data input into the inputterminal 169 and the pulse train Data output from the D flip-flopcircuit 174 is calculated by the exclusive-OR circuit 177 to generatethe pulse W shown in (c) of FIG. 5. Also, the exclusive-OR between thepulse train Data output from the D flip-flop circuit 174 and the pulsetrain Data output from the D flip-flop circuit 176 is calculated by theexclusive-OR circuit 178 to generate the pulse X shown in (d) of FIG. 5.Then, these pulses W, X are output from the output terminals 179, 180respectively to be supplied to the input terminals 181, 182 of thecharge pump unit 172.

[0014] The charge pump unit 172 comprises the inverter circuit 183 forinverting the pulse W input via the input terminal 181; the F-channelMOS transistor 184 for receiving the pulse W output from the invertercircuit 183 and for turning ON to pull up the voltage of its sourceterminal to the power supply voltage V_(DD) by the power supply voltageV_(DD) applied to its drain terminal while the pulse W is “1”, i.e., thepulse W is output from the output terminal 179 of the phase comparator171; the N-channel MOS transistor 185 for receiving the pulse X input tothe input terminal 182 via its gate terminal and for lowering thevoltage of the drain terminal to the ground voltage “0” V of its sourceterminal while this pulse X is “1”; the capacitor 186 for executing thecharging operation by the power supply voltage V_(DD) generated at thesource terminal of the P-channel MOS transistor 184 when the P-channelMOS transistor 184 is in its ON state and also for executing thedischarging operation by the ground voltage generated at the drainterminal of the N-channel MOS transistor 185 when the N-channel MOStransistor 185 is in its ON state; the resistor 187 operated togetherwith the capacitance of the capacitor 186 to decide the time constant ofthe charging/discharging operations: and the bypass capacitor 188 forattenuating a high frequency component.

[0015] Then, when the pulse W is output from the phase comparator 171and the inverted pulse of the pulse W is output from the invertercircuit 183, the P-channel MOS transistor 184 is turned ON and then thecharging/discharging circuit 189 consisting of the capacitor 186 and theresistor 187 is charged, When the pulse X is output from the phasecomparator 171, the N-channel MOS transistor 185 is turned ON and thenthe charging/discharging circuit 189 is discharged. Thus, as shown in(e) of FIG. 5, the voltage signal is generated in accordance with anamount of charge accumulated in the capacitor 186 of thecharging/discharging circuit 189, and then this voltage signal issupplied to the voltage-controlled oscillator 173 via the outputterminal 190.

[0016] While increasing the oscillating frequency in compliance with theincrease of the voltage value of the voltage signal output from thecharge pump unit 172 and also decreasing the oscillating frequency incompliance with the decrease of the voltage value of the voltage signal,the voltage-controlled oscillator 173 feeds back the clock signal Xck1,that is obtained by the oscillating operation, to the input terminal 170of the phase comparator 171 and also supplies this clock signal Xck1 tothe succeeding stage system (not shown).

[0017] Accordingly, in this PLL circuit 191, when the phase of the clocksignal Xck1 input into the input terminal 170 lags behind the phase ofthe discontinuous pulse train Data input into the input terminal 169,i.e., when the rise timing of the clock signal Xck1 lags behindrise/fall timings of the discontinuous pulse train Data, the width ofthe pulse W output from the phase comparator 171 is set wider than“0.5T” to expand the conduction period of the P-channel MOS transistor184. Thus, the amount of charge accumulated in the capacitor 186 of thecharging/discharging circuit 189 is increased gradually and accordinglythe oscillating frequency of the voltage-controlled oscillator 173 isincreased gradually.

[0018] Then, when the pulse train Data coincide in phase with the clocksignal Xck1, i.e., at a point of time when the width of the pulse Woutput from the phase comparator 171 becomes equal to “0.5T”, the amountof charge accumulated in the capacitor 186 of the charging/dischargingcircuit 189 is kept constant and accordingly the oscillating frequencyof the voltage-controlled oscillator 173 is fixed.

[0019] Then, in the situation that the pulse train Data whose pulsewidth is set to “T” is being input, when the phase of the clock signalXck1 goes ahead of the phase of the pulse train Data, i.e., when thefall timing of the clock signal Xck1 goes ahead of the rise/fall timingsof the discontinuous pulse train Data, the width of the pulse W outputfrom the phase comparator 171 is set narrower than “0.5T” to shorten theconduction period of the P-channel MOS transistor 184. Thus, the amountof charge accumulated in the capacitor 186 of the charging/dischargingcircuit 189 is decreased gradually and accordingly the oscillatingfrequency of the voltage-controlled oscillator 173 is decreasedgradually.

[0020] Then, when the pulse train Data coincide in phase with the clocksignal Xck1, i.e., at a point of time when the width of the pulse Woutput from the phase comparator 171 becomes equal to “0.5T”, the amountof charge accumulated in the capacitor 186 of the charging/dischargingcircuit 189 is kept constant and accordingly the oscillating frequencyof the voltage-controlled oscillator 173 is fixed. In contrast, sincethe exclusive-OR between the output of the D flip-flop circuit 174, thatis output at the leading edge of the clock signal Xck1, and the outputof the D flip-flop circuit 176, that is output substantially at thetrailing edge of the clock signal Xck1 when the circuit 176 receives theoutput of circuit 174, is calculated, the pulse width of the pulse X isalways set to 0.5T.

[0021] However, the above PLL circuit 191 in the prior art has theproblems described in the following.

[0022] First, in the phase comparator 171 of the PLL circuit 191 shownin FIG. 4, the value of the pulse train Data supplied to the data inputterminal D of the D flip-flop circuit 174 is received at the rise of theclock signal Xck1, and the value of the pulse train Data supplied to thedata input terminal D of the D flip-flop circuit 176 (the value of thepulse train Data supplied from the data output terminal Q of the Dflip-flop circuit 174) is received at the fall of the clock signal Xck1.Therefore, the pulse train Data output from the data output terminal Qof the D flip-flop circuit 176 lags behind the pulse train Data outputfrom the data output terminal Q of the D flip-flop circuit 174 by“0.5T”.

[0023] For this reason, the width of the pulse W output from theexclusive-OR circuit 177 can be changed from “0” to “1T” in answer tothe difference between the phase of the clock signal Xck1 and the phaseof the pulse train Data, nevertheless the width of the pulse X outputfrom the exclusive-OR circuit 178 is always kept at “0.5T”. That is, thewidth of the pulse X has merely a meaning as the reference width used todecide whether or not the width of the pulse W is shorter or longer than“0.5T”, on the charge pump unit 172 side.

[0024] Then, when the difference between the phase of the clock signalXck1 and the phase of the pulse train Data is “0”, i.e., at a point oftime when the phase coincides with each other, the widths of both thepulse W and the pulse X become “0.5T”. Therefore, at this time, theoutput can be reduced substantially to “0” by calculating a differencebetween a time-integral value of the width of the pulse W and atime-integral value of the width of the pulse X even if both the widthof the pulse W and the width of the pulse X are deviated. But theproblem is that occurrence times of the pulse W and the pulse X are notequal, and thus the pulsation of the voltage signal becomes largebecause the capacitor is charged in the period of the pulse W and isdischarged in the period of the pulse X.

[0025] As the countermeasure of this, if the value of the resistor 187and the value of the capacitor 186 both constituting the charge pumpunit 172 are increased to enlarge the time constant, variation in thevoltage value of the voltage signal can be reduced and thus the voltagesignal can come close to the direct current. But the responsibility,especially the transient responsibility becomes worse if to do so, andtherefore the value of the resistor 187 and the value of the capacitor186 can be increased merely to some extent.

[0026] In contrast, if the value of the resistor 187 and the value ofthe capacitor 186 both constituting the time-constant circuit 189 arereduced to decrease the time constant, the transient responsibility canbe improved, but the pulsation of the voltage value of the voltagesignal is increased. Thus, the oscillating frequency of thevoltage-controlled oscillator 173 is not stabilized, and there is such apossibility that the jitter, the false drawing, etc. occur.

[0027] Assume that, as particular numerical values, as shown in FIG. 6,for example, the capacitance of the capacitor 188 constituting thecharge pump unit 172 is set to “20 pF”, the capacitance of the capacitor186 is set to “0.047 μF”, the power supply voltage is set to “5 V”, thevalue of the resistor 187 is set to “390 Ω”, and the “0.5T” is set to “5ns”, and also charging/discharging currents of the P-channel MOStransistor 184 and the N-channel MOS transistor 185 are set to “200 μA”.Then, as shown in (e) of FIG. 5, the voltage value of the voltage signaloutput from the output terminal 190 of the charge pump unit 172 has thelarge pulsation.

[0028] In addition, if the waveform of this voltage signal is checked,the voltage value is largely varied at the portion where the pulse trainData is missed like the tooth missing. Therefore, the voltage value ofthe voltage signal is varied according to the pattern of the pulse trainData, and thus there is the possibility that the vicious jitter iscaused,

[0029] Also, it is difficult to make the charge current of the P-channelMOS transistor 184 and the discharge current of the N-channel MOStransistor 185 equal perfectly. Thus, when any one of the P-channel KOStransistor 184 and the N-channel MOS transistor 185, e.g., the chargecurrent of the P-channel MOS transistor 184 is slightly larger than thedischarge current of the N-channel MOS transistor 185, the chargeaccumulated in the capacitor 186 cannot be discharged completely, asshown in (e) of FIG. 5. Therefore, although both the width of the pulseW and the width of the pulse X are “0.5T”, the offset is generated andthe voltage value of the voltage signal Is deviated from the propervalue.

[0030] Such problem is the problem common to the phase comparators 171,159, 168 (see FIG. 2, FIG. 3, and FIG. 4) in which the occurrence timeof the pulse W and the occurrence time of the pulse X are different.

[0031] Also, in the phase comparator 171 employed in such PLL circuit191, the width of the pulse W can be changed from “0” to “1T” inaccordance with the difference between the phase of the clock pulse Xck1and the phase of the pulse train Data, nevertheless the capacitor 186 ofthe time-constant circuit is discharged in the period of “0.5T” by thepulse X, that is output after the pulse W and has the width of “0.5T”,even after such capacitor 186 Is charged in the period of “1T” when thewidth of the pulse W becomes “1T”. As a consequence, there is thedrawback that the capacitor 186 cannot be charged up to the power supplyvoltage “V_(DD)” and thus the output of the charge pump unit 172 cannotbe increased.

[0032] Therefore, as the phase comparator to overcome the problem due tothe employment of such phase comparator 171, etc. in the prior art,there is the phase comparator 192 in which the width of the pulse beingoutput at the phase coincidence point can be set as small as possibleand the occurrence time can be set to coincide with each other, as shownin FIG. 7 (Dan H. Wolaver, Phase Locked Loop Circuit Design, p.62). Suchphase comparator 192 is extensively employed as the phase comparator forthe continuous pulse without missing pulses.

[0033] The phase comparator 192 shown in FIG. 7 comprises the Dflip-flop circuit 193 for acquiring the “1” signal being input into thedata input terminal D every time when the differentiated pulse trainData_Dif (the pulse train obtained by differentiating the pulse trainData) is input into the clock terminal, and outputting this signal fromthe data output terminal Q while holding this signal, and then resettingthe held content to output the “0” signal from the data output terminalQ every time when the “1” signal is input into the reset terminal R: theD flip-flop circuit 194 for acquiring the “1” signal input into the datainput terminal D every time when the clock signal Xck1 input into theclock terminal rises, and outputting this signal from the data outputterminal Q while holding this signal, and then resetting the heldcontent to output the “0” signal from the data output terminal Q everytime when the “1” signal is input into the reset terminal R; and the ANDcircuit 195 for generating the “1” signal to reset the D flip-flopcircuits 193, 194 when the “1” signal is output from the data outputterminal Q of the D flip-flop circuit 194 and also the “1” signal isoutput from the data output terminal Q of the D flip-flop circuit 193.

[0034] Then, as shown in (a) of FIG. 8, in the situation that the pulsetrain Data whose pulse width is set to “T” is supplied and also thedifferentiated pulse train Data_Dif obtained by differentiating thepulse train Data is input, when the phase of the differentiated pulsetrain Data_Dif coincides with the phase of the clock signal Xck1, asshown in (b) (c) of FIG. 8, the pulses U5, D5 that have the narrow widthand are synchronized with each other are generated from the data outputterminals D of the D flip-flop circuits 193, 194 respectively to causethe charge pump unit to execute the charging operation and thedischarging operation, as shown in (d) (e) of FIG. 8.

[0035] However, as shown in (a) to (e) of FIG. 8, in this phasecomparator 192, the excellent function can be achieved with respect tothe continuous pulse train Data with no missing pulse like the pulsetrain Data shown in the periods A1, A2, A3, A4, A5, nevertheless theerroneous pulse (false pulse) is output as the pulse DS when thedifferentiated pulse train Data_Dif obtained by differentiating thepulse train Data with the missing pulse such as the pulse train Datashown in the periods B1, B2, B3, i.e., the pulse train Data with onemissing pulse, the pulse train Data with two missing pulses, the pulsetrain Data with three missing pulses, etc. is input.

[0036] This is because the D flip-flop circuit 194 reads and outputs “1”at the time point of the rise of the clock signal Xck1, e.g., at thetime of point P1 in FIG. 8 in the pulse missing period but the output ofthe D flip-flop circuit 193 has already been reset to “0”, thus thereset by the AND circuit 195 cannot be satisfied, thus the output of theD flip-flop circuit 194 is still kept at “1” until the rising timepoints of the succeeding differentiated pulse train Data_Dif and theclock signal Xck1, and therefore the false pulse having the wide widthis output.

[0037] Accordingly, there is the drawback that such phase comparator 192cannot handle the pulse train Data with missing pulses,

SUMMARY OF THE INVENTION

[0038] The present invention has been made in view of the abovecircumstances, and it is an object of the present invention to provide aphase comparator which is capable of generating a precise phase-comparedoutput for a pulse train that Is modulated by the data into the toothmissing state, minimizing ripple of a detected output to reduce as closeto zero as possible when frequencies and phases coincide with eachother, increasing a variable range of the detected output, reducingjitters to enable a high speed response, and having a frequencydiscriminating function, and a synchronizing signal extracting deviceusing the same.

[0039] In order to achieve the above object, according to an aspect ofthe present invention, there is provided a phase comparator comprising:a phase comparing portion for generating a leading phase instructingpulse and a lagging phase instructing pulse to mate a phase of an inputpulse train and a phase of an input clock signal with each other inaccordance with the phases; a correction pulse generating portion forgenerating a correction pulse in accordance with the input pulse trainand the input clock signal; and a resetting portion for resetting thephase comparing portion by generating a reset pulse in accordance withthe leading phase instructing pulse and the lagging phase instructingpulse output from the phase comparing portion, the correction pulseoutput from the correction pulse generating portion, and the input clocksignal.

[0040] In order to achieve the above object, according to another aspectof the present invention, there is provided a phase comparatorcomprising: a phase comparing portion for generating a leading phaseinstructing pulse and a lagging phase instructing pulse to mate a phaseof an input pulse train and a phase of an input clock signal with eachother in accordance with the phases; a correction pulse generatingportion for generating a correction pulse in accordance with the inputpulse train and the input clock signal; a resetting portion forresetting the phase comparing portion by generating a reset pulse inaccordance with the leading phase instructing pulse and the laggingphase instructing pulse output from the phase comparing portion, thecorrection pulse output from the correction pulse generating portion,and the input clock signal; and a pulse correcting portion for removingfalse pulses contained in the lagging phase instructing pulse outputfrom the phase comparing portion, based on the correction pulse outputfrom the correction pulse generating portion.

[0041] In a preferred embodiment of the present invention, thecorrection pulse generating portion generates the correction pulse thathas a pulse width equivalent to a time period from a time at which thecorrection pulse is triggered by the clock signal to a time at which thecorrection pulse is reset by a differentiated pulse train obtained bydifferentiating the pulse train, and detects a pulse missing of theinput pulse train based on the pulse width of the correction pulse.

[0042] In a preferred embodiment of the present invention, thecorrection pulse generating portion generates the correction pulse thathas a pulse width equivalent to a time period obtained by overlapping atime period from a time at which the correction pulse is triggered bythe clock signal to a time at which the correction pulse is reset by adifferentiated pulse train obtained by differentiating the pulse trainand a time period from a time at which the correction pulse is triggeredby a second clock signal that lags behind the clock signal by apredetermined degrees to a time at which the correction pulse is resetby a differentiated pulse train obtained by differentiating the pulsetrain, and detects a pulse missing of the input pulse train based on thepulse width of the correction pulse.

[0043] In a preferred embodiment of the present invention, the phasecomparing portion includes a first flip-flop circuit triggered by adifferentiated pulse train obtained by differentiating the pulse trainto output the leading phase instructing pulse and a second flip-flopcircuit triggered by the clock signal to output the lagging phaseinstructing pulse, and the resetting portion generates a reset pulsewhen both the leading phase instructing pulse and the lagging phaseinstructing pulse are output from the phase comparing portion or whenthe clock signal is input in a situation that the correction pulse isbeing output from the correction pulse generating portion, and resetsthe leading phase instructing pulse and the lagging phase instructingpulse by resetting the respective flip-flop circuits constituting thephase comparing portion.

[0044] In a preferred embodiment of the present invention, the phasecomparing portion includes a first flip-flop circuit triggered by adifferentiated pulse train obtained by differentiating the pulse trainto output the leading phase instructing pulse and a second flip-flopcircuit triggered by the clock signal to output the lagging phaseinstructing pulse, and the resetting portion generates a reset pulsewhen both the leading phase instructing pulse and the lagging phaseinstructing pulse are output from the phase comparing portion, andresets the leading phase instructing pulse and the lagging phaseinstructing pulse by resetting the respective flip-flop circuitsconstituting the phase comparing portion; or generates a reset pulsewhen the clock signal is input in a situation that the correction pulseis being output from the correction pulse generating portion and resetsthe lagging phase instructing pulse by resetting the second flip-flopcircuit constituting the phase comparing portion.

[0045] In a preferred embodiment of the present invention, the phasecomparing portion generates the leading phase instructing pulse and thelagging phase instructing pulse by using a differentiated pulse trainobtained by differentiating both of a rise and a fall of the pulsetrain, and selects and outputs portions that correspond to at least oneof a high level period and a low level period of the pulse train fromthe leading phase instructing pulse and the lagging phase instructingpulse.

[0046] In order to achieve the above object, according to still anotheraspect of the present invention, there is provided a synchronizingsignal extracting device comprising: a phase comparator set forth in thefirst aspect of the present; a differentiator for differentiating anpulse train having a frequency that is ½ of a frequency of the Inputpulse train, and supplying to the phase comparator as the input pulsetrain; a charge pump unit for increasing a voltage value of an outputvoltage signal by executing a charging operation when the leading phaseinstructing pulse is input from the phase comparator, and decreasing thevoltage value of the output voltage signal by executing a dischargingoperation when the lagging phase instructing pulse is input from thephase comparator: and a voltage-controlled oscillator for receiving thevoltage signal output from the charge pump unit, generating a clocksignal having a frequency that increases as the voltage value of thevoltage signal increases, and supplying the generated clock signal tothe phase comparator.

[0047] In order to achieve the above object, according to yet stillanother aspect of the present invention, there is provided asynchronizing signal extracting device comprising: a phase comparatorset forth in the second aspect of the present invention; adifferentiator for differentiating an pulse train having a frequencythat is ½ of a frequency of the input pulse train, and supplying to thephase comparator as the input pulse train; a charge pump unit forincreasing a voltage value of an output voltage signal by executing acharging operation when the leading phase instructing pulse is inputfrom the phase comparator, and decreasing the voltage value of theoutput voltage signal by executing a discharging operation when thelagging phase instructing pulse is input from the phase comparator; anda voltage-controlled oscillator for receiving the voltage signal outputfrom the charge pump unit, generating a clock signal having a frequencythat increases as the voltage value of the voltage signal increases, andsupplying the generated clock signal to the phase comparator.

[0048] According to the above configurations, the precise synchronizingsignal can be generated with respect to the pulse train that is broughtinto the tooth missing state due to a modulation by data, while reducingthe number of parts. Also, the pulsation of the detected output can beminimized as small as possible to zero at the point of time when thesynchronizing signal having the matched frequency and phase is obtained,and the variable range of the detected output can be expanded. As aresult, the frequency variable range of the synchronizing signal can beexpanded to enable the high speed response, and also the frequencydiscriminating function can be provided.

[0049] The nature, principle and utility of the invention will becomemore apparent from the following detailed description when read inconjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In the accompanying drawings:

[0051]FIG. 1 is a block diagram showing an example of a normal PLLcircuit;

[0052]FIG. 2 is a circuit diagram showing an example of a normal phasecomparator employed in the prior art;

[0053]FIG. 3 is a circuit diagram showing another example of a normalphase comparator employed in the prior art;

[0054]FIG. 4 is a circuit diagram showing an example of a PLL circuitemploying the phase comparator shown in FIG. 2;

[0055]FIG. 5 is a waveform diagram showing an example of an operation ofthe PLL circuit shown in FIG. 4;

[0056]FIG. 6 is a schematic circuit diagram showing an example ofparticular circuit constants of a charge pump unit shown in FIG. 4;

[0057]FIG. 7 is a circuit diagram showing an example of a phasecomparator proposed in the prior art;

[0058]FIG. 8 is a time chart showing an example of an operation of thephase comparator shown in FIG. 7;

[0059]FIG. 9 is a block diagram showing an example of a synchronizingsignal extracting device in the prior art;

[0060]FIG. 10 is a circuit diagram showing a detailed configuration ofthe synchronizing signal extracting device shown in FIG. 9;

[0061]FIG. 11 is circuit diagram showing a phase comparator and asynchronizing signal extracting device according to an embodiment of thepresent invention;

[0062]FIG. 12 is a time chart showing an example of an operationexecuted when a pulse train input into the synchronizing signalextracting device shown in FIG. 11 is synchronized with a clock signalgenerated by this synchronizing signal extracting device;

[0063]FIG. 13 is a schematic diagram showing an example of a waveformobtained when the pulse train input into the synchronizing signalextracting device shown in FIG. 11 is synchronized with the clock signalgenerated by this synchronizing signal extracting device;

[0064]FIG. 14 is a time chart showing an example of an operationexecuted when a phase of the differentiated pulse of the pulse traininput Into the synchronizing signal extracting device shown in FIG. 11lags behind a phase of the clock signal generated by this synchronizingsignal extracting device;

[0065]FIG. 15 is a time chart showing an example of an operationexecuted when a phase of the differentiated pulse of the pulse traininput into the synchronizing signal extracting device shown in FIG. 11leads ahead of a phase of the clock signal generated by thissynchronizing signal extracting device;

[0066]FIG. 16 is a time chart showing an example of an operationexecuted when a frequency of the local clock of voltage controlledoscillator (VCO) input into the synchronizing signal extracting deviceshown in FIG. 11 is increased by “10%”;

[0067]FIG. 17 is a time chart showing an example of an operationexecuted when a frequency of the local clock of voltage controlledoscillator (VCO) input into the synchronizing signal extracting deviceshown in FIG. 11 is decreased by “10%”;

[0068]FIG. 18 is a circuit diagram showing a phase comparator accordingto another embodiment of the present invention;

[0069]FIG. 19 is a circuit diagram showing a phase comparator accordingto still another embodiment of the present invention;

[0070]FIG. 20 is a block diagram showing a synchronizing signalextracting device according to yet still another embodiment of thepresent invention;

[0071]FIG. 21 is a circuit diagram showing a detailed configuration ofthe synchronizing signal extracting device shown in FIG. 20;

[0072]FIG. 22 is a time chart showing the case where frequencies andphases coincide with each other between a differentiated pulse of pulsetrain Data and a clock signal Xck;

[0073]FIG. 23 is a time chart showing the case where the clock signalXck goes ahead of the differentiated pulse of the pulse train Data by0.25T;

[0074]FIG. 24 is a time chart showing the case where the clock signalXck lags behind the pulse train Data by 0.25T; FIG. 25 is a time chartshowing the case where a frequency fxck of the clock signal Xck is sethigher than the bit clock frequency of the pulse train Data (twice ofmaximum density data frequency) (fxck=1.25 fb);

[0075]FIG. 26 is a time chart showing the case where the frequency fxckof the clock signal Xck is set lower than the frequency fb of the pulsetrain Data (fxck=({fraction (1/1.25)}) fb=0.8 fb);

[0076]FIG. 27 is a circuit diagram in which a method of resetting acorrecting pulse generating portion in the synchronizing signalextracting device shown in FIG. 21 is modified;

[0077]FIG. 28 is a time chart showing an operation executed when a falselock is caused in the synchronizing signal extracting device shown inFIG. 21: and

[0078]FIG. 29 is a time chart showing an operation not to cause thefalse lock in the modified synchronizing signal extracting device shownin FIG. 27;

[0079]FIG. 30 is a circuit diagram in which a correcting pulsegenerating portion in the synchronizing signal extracting device shownin FIG. 27 is modified;

[0080]FIG. 31 is a time chart showing the case where the clock signalXck leads in phase 0.2T than the differentiated pulse train Data_Dif sothat no false pulse appears in the signal of pulse DL1 in thesynchronizing signal extracting device shown in FIG. 27;

[0081]FIG. 32 is a time chart showing the case where the clock signalXck leads in phase 0.5T than the differentiated pulse train Data_Dif sothat false pulses appear in the signal of pulse DL1 in the synchronizingsignal extracting device shown in FIG. 27;

[0082]FIG. 33 is a time chart showing the case where the frequency ofthe clock signal Xck is higher than that of the differentiated pulsetrain Data_Dif so that false pulses appear In the signal of pulse DL1 inthe synchronizing signal extracting device shown in FIG. 27;

[0083]FIG. 34 is a time chart showing the case where the frequency ofthe clock signal Xck is higher than that of the differentiated pulsetrain Data_Dif so that false pulses appear in the signal of pulse DL1 inthe synchronizing signal extracting device shown in FIG. 27;

[0084]FIG. 35 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 30 where no false pulse appearseven when the clock signal Xck1 leads in phase 0.5T than thedifferentiated pulse train Data_Dif;

[0085]FIG. 36 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 30 where no false pulse appearseven when the frequency of the clock signal Xck1 is higher than that ofthe differentiated pulse train Data_Dif;

[0086]FIG. 37 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 30 where no false pulse appearseven when the frequency of the clock signal Xck1 is high 9/8 times thatof the differentiated pulse train Data_Dif;

[0087]FIG. 38 is a circuit diagram in which a correcting pulsegenerating portion in the synchronizing signal extracting device shownin FIG. 27 is modified:

[0088]FIG. 39 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 38 where no false pulse appearseven when the clock signal Xck1 leads in phase 0.5T than thedifferentiated pulse train Data_Dif:

[0089]FIG. 40 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 38 where no false pulse appearseven when the frequency of the clock signal Xck1 is as high as twicethat of the differentiated pulse train Data Dif;

[0090]FIG. 41 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 38 where no false pulse appearseven when the frequency of the clock signal Xck1 is as high as 9/8 timesthat of the differentiated pulse train Data_Dif; and

[0091]FIG. 42 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 38 where false pulses appearunder a certain condition of the frequencies of the clock signal Xck1and the differentiated pulse train Data_Dif and the delay time of thedelay circuits.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0092] Embodiments of the present invention will be explained in detailwith reference to the accompanying drawings hereinafter.

[0093] <<Explanation of Configuration>>

[0094]FIG. 11 is circuit diagram showing a phase comparator and asynchronizing signal extracting device employing this phase comparatoraccording to an embodiment of the present invention.

[0095] The synchronizing signal extracting device 1 shown in FIG. 11comprises a differentiator 3 for differentiating and inverting thediscontinuous pulse train Data being input Into an input terminal 2; aphase comparator 9 for comparing the frequency and the phase of thediscontinuous differentiated pulse train Data_Dif, that is output froman output terminal 4 of the differentiator 3 and then input into aninput terminal 5, with the frequency and the phase of the clock signalXck1 to generate pulses U4, D4 having a width in accordance with to thiscompared result, and then outputting them from output terminals 7, 8respectively; a charge pump unit 12 for increasing a voltage value of avoltage signal by executing a charging operation when the pulse U4 isoutput from the output terminal 7 of the phase comparator 9 and theninput into an input terminal 10, or reducing the voltage value of thevoltage signal by executing a discharging operation when the pulse D4 isoutput from the output terminal 8 of the phase comparator 9 and theninput into an input terminal 11; and a voltage-controlled oscillator 14for increasing the oscillating frequency in compliance with the increaseof the voltage value of the voltage signal being output from an outputterminal 13 of the charge pump unit 12 or decreasing the oscillatingfrequency in compliance with the decrease of the voltage value of thevoltage signal to then generate the clock signal Xck1.

[0096] Then, in this synchronizing signal extracting device 1, the phaseof the discontinuous input pulse train Data and the phase of thegenerated clock signal Xck1 are compared with each other, then theoscillating frequency and the phase of the voltage-controlled oscillator14 are controlled based on this compared result such that the phase ofthe discontinuous input pulse train Data can coincide with the phase ofthe clock signal Xck1, and the clock signal Xck1 which coincides Inphase with the discontinuous input pulse train Data is generated.

[0097] The differentiator 3 includes a delay circuit 15 and anexclusive-NOR circuit 16. The delay circuit 15 consists of atransmission line, a multi-stage gate circuit, an integrating circuitusing resistors, capacitors, etc., or the like, and receives thediscontinuous pulse train Data input into the input terminal 2 and thendelays it by a time, e.g., corresponding to the ½ width of the minimumpulse width. The exclusive-NOR circuit 16 calculates the exclusive-ORbetween the discontinuous pulse train Data input into the input terminal2 and the delayed pulse train Data output from the delay circuit 15,then generates the differentiated pulse train Data_Dif consisting of thepulses that have a width corresponding to the delay time of the delaycircuit 15 with respect to the width of the pulses in the pulse trainData and are inverted, and then outputs this from the output terminal 4to supply to the input terminal 5 of the phase comparator 9.

[0098] The phase comparator 9 includes a phase comparator portion 17, acorrecting pulse generating portion 18, a resetting portion 19, and apulse correcting portion 20. The phase comparator portion 17 comparesthe frequency and the phase of the differentiated pulse train Data_Difbeing input into the input terminal 5 with the frequency and the phaseof the clock signal Xck1 being input into the input terminal 6, and thengenerates a pulse U4 (leading phase instruction (charge instruction)pulse) or a pulse D4 a (lagging phase instruction (dischargeinstruction) pulse) in accordance with this compared result. Thecorrecting pulse generating portion 18 generates a correcting pulse Ebased on the clock signal Xck1 input into the input terminal 6 and thedifferentiated pulse train Data_Dif input into the input terminal 5. Theresetting portion 19 resets the phase comparator portion 17, based onthe pulse E output from the correcting pulse generating portion 18, theclock signal Xck1 input into the input terminal 6, and the pulses U4, D4a output from the phase comparator portion 17. The pulse correctingportion 20 removes the false pulse contained in the pulse D4 a by usingthe correcting pulse E, based on the pulse E being output from thecorrecting pulse generating portion 18.

[0099] The phase comparator portion 17 consists of two D flip-flopcircuits 21, 22. The D flip-flop circuit 21 acquires the “1” signalbeing Input into the data Input terminal D every time when thedifferentiated pulse train Data_Dif that is input into the clockterminal via the input terminal 5 is raised, and then outputs this “1”signal from the data output terminal Q while holding it and then resetsthe held content to then output the “0” signal from the data outputterminal Q every time when the “0” signal (the “1” signal in thenegative logic) is input into the reset terminal R. The D flip-flopcircuit 22 acquires the “1” signal being input into the data inputterminal D every time when the clock signal Xck1 that is input into theclock terminal via the input terminal 6 is raised, and then outputs this“1” signal from the data output terminal Q while holding it and thenresets the held content to then output the “0” signal from the dataoutput terminal Q every time when the “0” signal (the “1” signal in thenegative logic) is input into the reset terminal R.

[0100] The correcting pulse generating portion 18 includes an invertercircuit 23, and a D flip-flop circuit 24. The inverter circuit 23 is acircuit for inverting the clock signal Xck1 being input into the inputterminal 6. The D flip-flop circuit 24 acquires the “1” signal beinginput into the data input terminal D every time when the inverted clocksignal Xck1 output from the inverter circuit 23 is raised, and outputsthis signal from the data output terminal Q while holding this, and alsoresets the held content to then output the “0” signal from the dataoutput terminal Q every time when the differentiated pulse trainData_Dif input into the input terminal 5 is “1” and thus the “o” signal(the “1” signal in the negative logic) is input into the reset terminalR.

[0101] The resetting portion 19 includes two AND circuits 25, 26, and aNOR circuit 27, The AND circuit 25 calculates the logical product of thepulses U4, D4 a being output from the D flip-flop circuits 21, 22 of thephase comparator portion 17 respectively. The AND circuit 26 calculatesthe logical product of the clock signal Xck1 input into the inputterminal 6 and the pulse E output from the D flip-flop circuit 24 of thecorrecting pulse generating portion 18. The NOR circuit 27 calculatesthe logical sum of calculated results of the AND circuits 25, 26 andthen inverts it.

[0102] The pulse correcting portion 20 includes an inverter circuit 28and an AND circuit 29. The inverter circuit 28 Inverts the pulse E beingoutput from the D flip-flop circuit 24 of the correcting pulsegenerating portion 18. The AND circuit 29 calculates the logical productof the inverted signal of the pulse E output from the inverter circuit28 and the pulse D4 a output from the D flip-flop circuit 22 of thephase comparator 17, This pulse correcting portion 20 causes theinverter circuit 28 to invert the pulse E being output from the Dflip-flop circuit 24 of the correcting pulse generating portion 18, andacquires the pulse D4 a being output from the D flip-flop circuit 22 ofthe phase comparator 17 when the inverted signal of the pulse E is “1”,and then supplies this pulse to the input terminal 11 of the charge pumpunit 12 as the pulse D4. That is, D4 a is inhibited to output toterminal 8 during E is “1”.

[0103] The charge pump unit 12 includes an inverter circuit 30, aP-channel MOS transistor 31, an N-channel MOS transistor 32, a capacitor33, a resistor 34, and a capacitor 35. The inverter circuit 30 invertsthe pulse U4 input via the input terminal 10. The P-channel MOStransistor 31 receives the inverted signal of the pulse U4 output fromthe inverter circuit 30 via the gate terminal, and turns ON to pull thevoltage of the source terminal up to the power supply voltage V_(DD) byusing the power supply voltage V_(DD) applied to the drain terminalduring when the Inverted signal of the pulse U4 is “0”, i.e., when thepulse U4 is being output from the output terminal 7 of the phasecomparator 9. The N-channel MOS transistor 32 receives the pulse D4being input into the input terminal 11 via the gate terminal, and alsoreduces the voltage of the drain terminal to the ground voltage “0” ofthe source terminal during when this pulse D4 is “1”. The capacitor 33executes a charging operation by the power supply voltage V_(DD)generated at the source terminal of the P-channel MOS transistor 31 whenthe P-channel MOS transistor 31 is in its conductive state, and executesa discharging operation by the ground voltage generated at the drainterminal of the N-channel MOS transistor 32 when the N-channel MOStransistor 32 is in its conductive state. Also, the capacitor 33 has theoperation for holding the compared output voltage at the phasecoincidence point. The resistor 34 as well as the capacitance of thecapacitor 33 decides the time constant. The capacitor 35 is a bypasscapacitor that attenuates a high-frequency component, and stabilizes thevoltage value of the generated voltage signal.

[0104] While increasing the oscillating frequency in accordance with theincrease of the voltage value of the voltage signal output from thecharge pump unit 12 and also decreasing the oscillating frequency inaccordance with the decrease of the voltage value of the voltage signal,the voltage-controlled oscillator 14 feeds back the clock signal Xck1,that is obtained by the oscillating operation, to the input terminal 6of the phase comparator 9 and also supplies this clock signal Xck1 tothe succeeding stage system (not shown).

[0105] <<Explanation of Operation>>

[0106] Then, an operation of this synchronizing signal extracting devicewill be explained in detail with reference to the circuit diagram shownin FIG. 11 and time charts shown in FIG. 12 to FIG. 17 hereunder.

[0107] <The Case Where Phases of the Differentiated Pulse Train and theClock Signal Coincide with Each Other>

[0108] In FIG. 12, periods A11, A12, A13, A14, A15 show the state inwhich no missing pulse exists respectively, and periods B11, B12, B13shows the state in which one, two, and three pulses are missingrespectively.

[0109] The D flip-flop circuit 24 of the correcting pulse generatingportion 18 reads and outputs “1” when the clock signal Xck1 input intothe input terminal 6 is fallen down. and is reset to “0” during when thedifferentiated pulse train Data_Dif is low level “0”, that is obtainedby differentiating the pulse train Data input into the input terminal 2by the differentiator 3 and input into the input terminal 5.Accordingly, as shown by the pulse E in (d) of FIG. 12, in the periodssuch as B11, B12, B13, etc. in which the pulse missing occurs, thedifferentiated pulse train Data_Dif is “1” at the time of falling down,therefore the pulse having the wide width is generated corresponding tothe pulse missing period.

[0110] The D flip-flop circuit 21 is triggered at the rise of thedifferentiated pulse train Data_Dif input into the input terminal 5 andthus reads and outputs “1”. The D flip-flop circuit 22 is triggered atthe rising edge of the clock signal Xck1 input into the input terminal 6and thus reads and outputs “1”. Since the outputs of these D flip-flopcircuits 21, 22 are input into the AND circuit 25 of the resettingportion 19, both the D flip-flop circuits 21, 22 are reset via the NORcircuit 27 when both inputs of the AND circuit 25 are “1”. Likewise,since an output of the delayed flip-flop circuit 24, i.e., the pulse Eand the signal input into the input terminal 6. I.e., the clock signalXck1 are connected to the AND circuit 26 of the resetting portion 19,both the D flip-flop circuits 21, 22 are reset via the NOR circuit 27when both inputs of the AND circuit 26 are “1”.

[0111] Therefore, in the periods such as A11, A12, A13, etc. in which nopulse missing occurs, since the pulse E shown in (d) of FIG. 12 is “0”at the rise of the clock signal Xck1, only the AND circuit 25 and theNOR circuit 27 in the resetting portion 19 can function substantially.

[0112] Meanwhile, in the periods such as B11, B12, B13, etc. in whichthe pulse missing occurs, the D flip-flop circuit 21 reads and outputs“1” at the rise of the clock signal Xck1. However, since the pulse E is“1” and also the clock signal Xck1 is “1” in these periods, both the Dflip-flop circuits 21, 22 are reset via the AND circuit 26 and the NORcircuit 27 in the resetting portion 19. In this case, the D flip-flopcircuit 21 has already been reset, but no problem occurs even if thecircuit 21 is reset again, Thus, during missing pulse period, Dflip-flop 21 and 22 are both reset, so no decision is made by this phasecomparator. As a result, the output waveforms of the D flip-flopcircuits 21, 22 are given as the pulse U4 shown in (e) of FIG. 12 andthe pulse D4 a shown in (g) of FIG. 12.

[0113] However, in the pulse D4 a shown in (g) of FIG. 12, the pulseslabeled as the “false pulse” is generated In the pulse missing periodand thus do not correspond to the pulse U4 shown in (e) of FIG. 12, suchpulses must be removed. For this reason, in FIG. 11, the output of the Dflip-flop circuit 24, i.e., the pulse E is inverted by the invertercircuit 28 in the pulse correcting portion 20 and then connected to oneinput of the AND circuit 29 and the output of the D flip-flop circuit22, i.e., the pulse D4 a is connected to the other input of the ANDcircuit 29, and then the output of the AND circuit 29 is connected tothe output terminal 8 to serve as the pulse D4. According to suchconfiguration, as shown by the pulse D4 in (f) of FIG. 12, the falsepulse can be removed by inhibiting the output of the pulse D4 a duringwhen the pulse E is “1”, i.e. in the pulse missing period, so that thepulse D4 which corresponds to the pulse U4 can be generated. Since thepulse U4 and the pulse D4 are generated simultaneously and the pulsewidth is narrow, the pulsation of the voltage in the charge pump unit 12In the succeeding stage can be suppressed as small as possible and thusthe synchronizing device with the small jitter can be achieved.

[0114] Also, since the pulse U4 and the pulse D4 are generatedsimultaneously and the pulse width is narrow, the pulsation can besuppressed low even if there is difference between the charging currentand the discharging current of the P-channel MOS transistor 31 and theN-channel MOS transistor 32. FIG. 13 shows an output voltage that has anextremely small value when the resistance value of the resistor 34=390Ω, the capacitance value of the capacitor 33=0.047 μF, the capacitancevalue of the capacitor 35=20 pF, the voltage value of the power supplyV_(DD)=5 V, and the frequency=100 MHz, as shown In FIG. 11.

[0115] <The Case Where the Clock Signal Goes Ahead of the Pulse Train>

[0116]FIG. 14 shows the case where the phase of the clock signal Xck1goes ahead of the differentiated pulse train Data_Dif by 0.25T. In thiscase, since the rise of the clock signal Xck1 come earlier than the riseof the differentiated pulse train Data_Dif, the D flip-flop circuit 22shown in FIG. 11 reads “1” and outputs “1” earlier and then thedifferentiated pulse train Data_Dif rises, so that both the D flip-flopcircuits 21, 22 are reset.

[0117] Accordingly, the pulse width of the output pulse D4 a of the Dflip-flop circuit 22 is given by the width of (the phase differencebetween the rise of the clock signal Xck1 and the rise of thedifferentiated pulse train Data_Dif)+(operation delay times of theresetting portion 19, etc.). That is, the output has the pulse widththat is in proportion to the phase difference. In contrast, the pulsewidth of the output pulse U4 of the D flip-flop circuit 21 is given bythe narrow pulse width that corresponds to the operation delay times ofthe resetting portion 19, etc.

[0118] Also, since the false pulse can be removed from the pulse D4 a bythe above action of the pulse E to give the pulse D4, the pulse D4having the pulse width that is in proportion to the phase difference canbe obtained. In other words, since the pulse width of the pulse D4 shownin (f) of FIG. 14 is wider than the pulse U4 shown in (e) of FIG. 14,the output is generated to lag the phase by lowering the voltage of theoutput terminal 13 via the charge pump unit 12 and lowering thefrequency of the voltage-controlled oscillator 14. As a result, theoutput of the charge pump unit 12 is also in proportion to this phasedifference.

[0119] <The Case Where the Clock Signal Lags Behind the Pulse Train>

[0120]FIG. 15 shows the case where the phase of the clock signal Xck1lags behind the differentiated pulse train Data_Dif by 0.25T oppositelyto the above. Since the D flip-flop circuit 21 reads and outputs “1”earlier than the D flip-flop circuit 22 conversely, and the pulse widthof the pulse U4 shown in (e) of FIG. 14 becomes wider, so that theoutput is generated to increase the frequency of the voltage-controlledoscillator 14 and to advance the phase. In this case, since the pulsewidth of the pulse U4 is in proportion to the phase difference betweenthe differentiated pulse train Data_Dif and the clock signal Xck1, theoutput of the charge pump unit 12 is also in proportion to the phasedifference.

[0121] <The Case Where the Frequency of the Clock Signal is Changed by“±10%”>

[0122]FIG. 16 shows the case where the frequency of the clock signalXck1 is higher than the frequency of the pulse train Data by 10%. Thepulse U4 shown in (d) of FIG. 16 has the minimum pulse width, and thepulse P4 shown in (e) of FIG. 16 has the wider pulse width. Thus, onlythe output is generated to lower substantially the frequency.

[0123] In contrast, FIG. 17 shows the case where the frequency of theclock signal Xck1 is lower than the frequency of the pulse train Data by10%. The pulse D4 shown in (e) of FIG. 17 has the minimum pulse width,and the pulse U4 shown in (d) of FIG. 17 has the wider pulse width.Thus, only the output is generated to increase substantially thefrequency.

[0124] Accordingly, the device shown in FIG. 11 as the embodiment of thepresent invention has not only the phase comparing function but also thefrequency discriminating function. The device having above two functionsis very excellent as the synchronizing device.

[0125] In other words, if the frequencies are separated away from eachother, the frequency acquisition (also called “frequency pulling-in”)for matching the frequency can be achieved only by the phase comparingfunction, but there are the disadvantages that much time might berequired to acquire the frequency and that the operation is trapped inthe middle of the frequency acquisition by the noise, etc. and cannot goout of such trap. In contrast, in the synchronizing device having thefrequency discriminating function in the present invention, it ispossible to acquire (to pull in) the frequency in a very short time andto make the phase equal. In addition, as shown in FIG. 16 and FIG. 17,even if the tooth missing state is present in the input pulse train, theoutput to respond to the frequency level can be generated surelyaccording to the frequency level without the influence of such toothmissing state.

[0126] <<Advantages>>

[0127] In this manner, in this embodiment, the frequency and the phaseof the differentiated pulse train Data_Dif input into the input terminal5 are compared with the frequency and the phase of the clock signal Xck1input into the input terminal 6 while generating the correcting pulse Ebased on the clock signal Xck1 input into the input terminal 6, then thepulses U4, D4 a are generated based on this compared result, then thefalse pulses contained in the pulse D4 a are removed by using thecorrecting pulse E when the tooth missing state is present in thedifferentiated pulse train Data_Dif input into the input terminal 5, andthen only the precise pulses U4, D4 are output from the output terminals7, 8. Therefore, the precise clock signal Xck1 can be generated withrespect to the pulse train Data, that is modulated by the data toproduce the tooth missing state, while reducing the number of parts, andalso the pulsation of the voltage signal can be minimized as small aspossible to zero not to generate the jitter, etc. at a point of timewhen the clock signal Xck1 having the matched frequency and phase isobtained.

[0128] Also, the pulse U4 output from the phase comparator 9 can besynchronized with the pulse D4, and also at least one of the pulse U4and pulse D4 can be reduced to the minimum width at the phasecoincidence point. Accordingly, the variable range of the voltage signaloutput from the charge pump unit 12 can be expanded. That is, a ratio ofthe output voltage of the operation point to the output voltage of phasecoincidence point, i.e., a figure of merit indicating the performance ofthe phase comparator can be maximized.

[0129] In addition, the high frequency discriminating function can beprovided to the phase comparator 9, and thus the operation in thefrequency acquiring stage such as the power supply ON stage, etc. can bemade advantageous.

[0130] Further, in this embodiment, even when the frequency and thephase of respective pulses constituting the pulse train Data coincidewith the frequency and the phase of the clock signal Xck1 output fromthe voltage-controlled oscillator 14 and also the rise timing of thedifferentiated pulse train Data_Dif output from the exclusive-NORcircuit 16 in the differentiator 3 coincide with the rise timing of theclock signal Xck1 output from the voltage-controlled oscillator 14, theP-channel MOS transistor 31 and the N-channel MOS transistor 32 in thecharge pump unit 12 can be operated by outputting the pulses U4, D4having extremely narrow widths that differ from each other by a valuethat corresponds to the phase difference. Therefore, the difference canbe provided between the conduction time of the P-channel MOS transistor31 and the conduction time of the N-channel MOS transistor 32 by thedifference (phase difference) between the rising timing of thedifferentiated pulse train Data_Dif output from the exclusive-NORcircuit 16 in the differentiator 3 and the rising timing of the clocksignal Xck1 output from the voltage-controlled oscillator 14. As aresult, the dead band can be eliminated and the response characteristiccan be improved.

[0131] In this embodiment, when the pulse train Data input into theinput terminal 2 is in the tooth missing state, the false pulses arepresent in the pulse D4 output from the phase comparator 9 and suchfalse pulses are removed by the pulse correcting portion 20. However, inthe system in which the restrict phase comparison is not needed, thefalse pulses having the extremely narrow width may be output as they areby omitting such pulse correcting portion 20.

[0132] <<Another Embodiment>>

[0133] In the above embodiment, when the pulse U4 is output from the Dflip-flop circuit 21 constituting the phase comparator portion 17 andalso the pulse D4 a is output from the D flip-flop circuit 22, or whenthe pulse E is output from the D flip-flop circuit 24 in the correctingpulse generating portion 18 and also the clock signal Xck1 input intothe input terminal 6 is raised, the D flip-flop circuits 21, 22constituting the phase comparator portion 17 are reset by the resettingportion 19 in the phase comparator 9. A phase comparator 41 may beconstructed by using other resetting portion, for example, a resettingportion 40 having a configuration shown in FIG. 18.

[0134] The resetting portion 40 shown in FIG. 18 comprises an ANDcircuit 42 for calculating a logical product between the pulses U4, D4 aoutput from the data output terminals D of the D flip-flop circuits 21,22 constituting the phase comparator portion 17; an inverter circuit 43for inverting the calculated result of the AND circuit 42 to supply itto the reset terminal R of the D flip-flop circuit 21; an AND circuit 44for calculating a logical product between the clock signal Xck1 inputinto the input terminal 6 and the pulse E output from the data outputterminal D of the D flip-flop circuit 24 constituting the correctingpulse generating portion 18; and a NOR circuit 45 for calculating alogical sum between calculated results of the AND circuits 42, 44 andthen inverting it to supply to the reset terminal R of the D flip-flopcircuit 22. When both the pulses U4, D4 a output from the D flip-flopcircuits 21, 22 In the phase comparator portion 17 are “1”, the Dflip-flop circuits 21, 22 are reset by generating the “0” signal (the“1” signal in the negative logic). When the clock signal Xck1 input intothe input terminal 6 is “1” in the situation that the pulse E outputfrom the D flip-flop circuit 24 in the correcting pulse generatingportion 18 is “1”, the “0” signal (the “1” signal in the negative logic)is generated to reset only the D flip-flop circuit 22 in the phasecomparator portion 17.

[0135] When the pulse train Data is in the tooth missing state even ifsuch resetting portion 40 is employed, the D flip-flop circuit 22 can bereset. Accordingly, while reducing the cost of the overall system byusing the general part, the precise clock signal Xck1 can be generatedwith respect to the pulse train Data that is brought into the toothmissing state due to a modulation by data. Also, the pulsation of thevoltage signal can be minimized as small as possible to zero at a pointof time when the clock signal Xck1 having the matched frequency andphase is obtained, and the variable range of the detected output can beexpanded. As a result, the frequency variable range of the clock signalXck1 can be expanded to enable the high speed response, and also thefrequency discriminating function can be provided.

[0136] Also, in this embodiment, even when the frequency and the phaseof respective pulses constituting the pulse train Data coincide with thefrequency and the phase of the clock signal Xck1 output from thevoltage-controlled oscillator 14 and also the rise timing of thedifferentiated pulse train Data_Dif output from the exclusive-NORcircuit 16 in the differentiator 3 coincide with the rise timing of theclock signal Xck1 output from the voltage-controlled oscillator 14. theP-channel MOS transistor 31 and the N-channel MOS transistor 32 in thecharge pump unit 12 can be operated by outputting the pulses U4, D4having extremely narrow widths that differ from each other by a valuethat corresponds to the phase difference. Therefore, the difference canbe provided between the conduction time of the P-channel MOS transistor31 and the conduction time of the N-channel MOS transistor 32 by thedifference (phase difference) between the rising timing of thedifferentiated pulse train Data_Dif output from the exclusive-NORcircuit 16 in the differentiator 3 and the rising timing of the clocksignal Xck1 output from the voltage-controlled oscillator 14. As aresult, the dead band can be eliminated and the response characteristiccan be improved.

[0137] In this embodiment, when the pulse train Data input into theinput terminal 2 is brought into the tooth missing state, the falsepulses are present in the pulse D4 output from the phase comparator 41and such false pulses are removed by the pulse correcting portion 20.However, in the system in which the restrict phase comparison is notneeded, the false pulses having the extremely narrow width may be outputas they are by omitting such pulse correcting portion 20.

[0138] <Still Another Embodiment>>

[0139] Also, in the above embodiment, when the pulse E is output fromthe D flip-flop circuit 24 in the correcting pulse generating portion18, the AND circuit 29 is brought into its pulse-passing inhibit stateby inverting this pulse E by virtue of the inverter circuit 28 in thepulse correcting portion 20. Thus, even if the false pulses D4 a areoutput from the D flip-flop circuit 22 in the phase comparator portion17, the false pulses D4 a are prevented from being output to the chargepump unit 12. However, as shown in FIG. 19, if a phase comparator 50 inwhich the inverted signal of the clock signal Xck1 output from theinverter circuit 23 in the correcting pulse generating portion 18 isdirectly input into the AND circuit 26 of the resetting portion 19 isemployed, the false pulse D4 a can be prevented from being output fromthe D flip-flop circuit 22 in the phase comparator 17, and thus thepulse correcting portion 20 may be omitted.

[0140] When the pulse train Data is brought into the tooth missing stateeven if such phase comparator 50 is employed, the D flip-flop circuits21, 22 can be reset to prevent the malfunction. Accordingly, like theabove embodiment, while reducing mostly the number of parts, the preciseclock signal Xck1 can be generated with respect to the pulse train Datathat is brought into the tooth missing state due to a modulation bydata. Also, the pulsation of the voltage signal can be minimized assmall as possible to zero at a point of time when the clock signal Xck1having the matched frequency and phase is obtained, and the variablerange of the detected output can be expanded. As a result, the frequencyvariable range of the clock signal Xck1 can be expanded to enable thehigh speed response, and also the frequency discriminating function canbe provided.

[0141] Also, in this embodiment, even when the frequency and the phaseof respective pulses constituting the pulse train Data coincide with thefrequency and the phase of the clock signal Xck1 output from thevoltage-controlled oscillator 14 and also the rise timing of thedifferentiated pulse train Data_Dif output from the exclusive-NORcircuit 16 in the differentiator 3 coincide with the rise timing of theclock signal Xck1 output from the voltage-controlled oscillator 14, theP-channel MOS transistor 31 and the N-channel MOS transistor 32 in thecharge pump unit 12 can be operated by outputting the pulses U4, D4having extremely narrow widths that differ from each other by a valuethat corresponds to the phase difference. Therefore, the difference canbe provided between the conduction time of the P-channel MOS transistor31 and the conduction time of the N-channel MOS transistor 32 by thedifference (phase difference) between the rising timing of thedifferentiated pulse train Data_Dif output from the exclusive-NORcircuit 16 in the differentiator 3 and the rising timing of the clocksignal Xck1 output from the voltage-controlled oscillator 14. As aresult, the dead band can be eliminated and the response characteristiccan be improved.

[0142] Furthermore, the inverter circuit 23 constituting the correctingpulse generating portion 18 in the phase comparator shown in above FIG.11, FIG. 18, and FIG. 19 may be replaced with the delay circuit or thedelay element having the same function as the delay circuit 15.

[0143] Also, in the above embodiment, the differentiator 3 consists ofthe delay circuit 15 for delaying the pulse train Data, and theexclusive-NOR circuit 16 for calculating the exclusive-NOR between theoutput of the delay circuit 15 and the pulse train Data. But the presentinvention is not limited to this. This is because distortion of thepulse width is caused according to the transmitting medium, and thus therise and the fall of the input pulse train Data are distorted, andtherefore the phase comparison employing both the rise and the fall ofthe pulse train Data is affected by the jitter.

[0144] The differentiator 3 may consist of the delay circuit 15 fordelaying the pulse train Data, the inverter circuit for inverting theoutput or the delay circuit 15, and the NAND circuit for calculatingNAND between the output of this inverter circuit and the pulse trainData, and then the output of this NAND circuit may be used as the output(the differentiated pulse train Data_Dif) of the differentiator 3.According to this configuration, the precise phase comparison that canreduce the influence of the jitter, although the number of comparisontimes is reduced by half, can be achieved by executing the phasecomparison employing any one of the rise and the fall of the pulse trainData.

[0145] <<Yet Still Another Embodiment>>

[0146] Next, a yet still another embodiment of the present inventionwill be explained hereunder.

[0147] First, the concept of this embodiment will be explained withreference to FIG. 9 and FIG. 10 in the prior art hereunder.

[0148] As shown in a block diagram of FIG. 9, the synchronizing signalextracting device in the prior art comprises a rise differentiatingcircuit 202, a clock control circuit 203, a phase/frequency comparator204, a charge pump unit 205, and a voltage-controlled oscillator 206.Then, the signal obtained by differentiating only the rise of the datapulse train by the rise differentiating circuit 202 is supplied to oneinput of the phase/frequency comparator 204, and the clock signalcontrolled by the clock control circuit 203, that outputs the localclock signal in connection with the rise differentiated signal only whenthe rise differentiated signal is generated, is supplied to the otherinput of the phase/frequency comparator 204. Thus, the phase and thefrequency between the above input rise differentiated signal and theclock signal can coincide with each other.

[0149]FIG. 10 shows a detailed circuit example of the abovesynchronizing signal extracting device shown in FIG. 9 in the prior art.The rise differentiating circuit 202 includes a delay circuit 144constructed by connecting in parallel a plurality of delay elements 143,and an exclusive-OR circuit 145. A reference 141 is a rise trigger-typeD flip-flop circuit. Then, the data input pulse train isfrequency-divided into ½ by the rise trigger-type D flip-flop circuit141 to generate the pulse Q, and then this pulse Q is differentiated bythe delay circuit 144 and the exclusive-OR circuit 145. Accordingly, thesignal obtained by differentiating only the rise of the data pulse train(rise differentiated signal) is supplied to the phase/frequencycomparator 204.

[0150] Also, a clock control circuit 203 includes an inverter circuit122, two D flip-flop circuits 123, 125, and an exclusive-OR circuit 127.Then, the pulse Q that is obtained by ½-frequency-dividing the datapulse train is supplied from the D flip-flop circuit 141 to the datainput terminal of the D flip-flop circuit 123, and also the local clocksignal VCO CLOCK is supplied to the clock input terminal. In this case,the clock control circuit 203 has the same circuit configuration as thatshown in FIG. 2. This clock control circuit 203 can operate to supplythe local clock signal VCO CLOCK to the phase/frequency comparator 204only at the point of rise time of the input data pulse train.

[0151] The phase/frequency comparator 204 includes two D flip-flopcircuits 128, 129, and an AND circuit 130. In this case, thisphase/frequency comparator 204 has the same circuit configuration andthe same operation as those shown in FIG. 7. Accordingly, even if thetooth missing is caused in the input data pulse train, the normal phasecomparison output can be generated without the false output in the phasecomparing stage In which the frequency has already been matched.However, in this example in the prior art, there is the problem that,since the false pulling is caused according to the frequency in thefrequency pulling stage, the frequency pulling range cannot be expanded.

[0152] In this embodiment of the present invention, the above drawbackin the prior art can be overcome by selecting only any one of the highlevel period and the low level period of the input data pulse train orboth of the high level period and the low level period.

[0153] That is, as shown in a block diagram of FIG. 20, a synchronizingsignal extracting device 301 in this embodiment comprises a rise/falldifferentiating circuit 302, a phase/frequency comparator 303, acorrecting circuit 304, a charge pump unit 305, and a voltage-controlledoscillator 306. The output signal of the rise/fall differentiatingcircuit 302 of the input data pulse train is supplied to one input ofthe phase/frequency comparator 303, and the local clock signal outputfrom the voltage-controlled oscillator 306 is input into the other inputof the phase/frequency comparator 303 as it is. Also, the input datapulse train, the output signal of the rise/fall differentiating circuit302, and the local clock signal are supplied to the correcting circuit304 that is connected to the outputs of the phase/frequency comparator303. The outputs of the correcting circuit 304 (a leading phaseinstructing pulse after the correction, a lagging phase instructingpulse after the correction), that are obtained by correcting the outputsof the phase/frequency comparator 303, are supplied to the charge pumpunit 305.

[0154] Then, a particular circuit configuration of the synchronizingsignal extracting device 301 shown in FIG. 20 will be explained withreference to FIG. 21 hereunder. In FIG. 21, the same references areaffixed to the same constituent parts as those in FIG. 11, and theirexplanation will be omitted herein. As for the correlation between FIG.20 and FIG. 21, the rise/fall differentiating circuit 302 corresponds tothe differentiator 3; the phase/frequency comparator 303 corresponds tothe phase comparator 17: the correcting circuit 304 corresponds to thecorrecting pulse generating portion 18, the correcting portion 20 andthe resetting circuit 19; the charge pump unit 305 corresponds to thecharge pump unit 12; and the voltage-controlled oscillator 306corresponds to the voltage-controlled oscillator 14.

[0155] In this embodiment, as shown in FIG. 21, three-input AND circuit29 is provided, and an AND circuit 37 is provided to supply the outputof the D flip-f lop circuit 21 to the charge pump unit 12. Also, aswitch 39 having three contacts 40, 41, 42 is provided. The middle point43 of the switch 39 is connected to inputs of the AND circuit 29 and theAND circuit 37 respectively. The signal of the logical level “1” issupplied to the contact 40 of three contacts of the switch 39, the pulsetrain Data is supplied to the contact 41, and the inverted signal of thepulse train Data is supplied to the contact 42 via the inverter circuit38. In this case, a NAND circuit may be constructed by combining the ANDcircuit 37 and the inverter circuit 30 of the charge pump unit 12.

[0156] In the above configuration, the differentiated pulse trainData_Dif, that is obtained by differentiating the rise and fall of thepulse train Data, and the clock signal Xck as it is are input into thephase comparator 9. Since the operations of the phase comparator 17, thecorrecting pulse generating portion 18, and the resetting circuit 19 areidentical to those in FIG. 11 mentioned above, their explanation will beomitted herein.

[0157] Next, an operation of the switch 39 will be explained hereunder.

[0158] First, when the middle point of the switch 39 is connected to thecontact 40, the signal of the logical level “1” is supplied to the ANDcircuit 37 and the AND circuit 29. Therefore, the pulse UL1 a(corresponding to the pulse U4 in FIG. 11) is output from the outputterminal 7 of the phase comparator 9, and the logical product of thepulse DL1 a and the inverted signal of the pulse E (corresponding to thepulse D4 in FIG. 11) is output from the output terminal 8.

[0159] Then, when the middle point 43 of the switch 39 is connected tothe contact 41, the pulse train Data is supplied to the AND circuit 37and the AND circuit 29. Therefore, the output pulse UL1 a of the phasecomparator 9 and the logical product of the pulse DL1 a and the invertedsignal of the pulse E in the high level period of the pulse train Dataare output from the output terminal 7 and the output terminal 8. Then,when the middle point 43 of the switch 39 is connected to the contact42, only the outputs of the phase comparator 9 in the low level periodof the pulse train Data are selected and then output from the outputterminal 7 and the output terminal 8 as the output pulse UL1 and theoutput pulse DL1 respectively.

[0160]FIG. 22 to FIG. 26 are time charts showing the pulse train Data,the differentiated pulse train Data_Dif, the clock signal Xck; the pulseU4 and the pulse D4 shown in FIG. 11; the pulse UL1 and the pulse DL1shown in FIG. 21; and the pulse UL2 and the pulse DL2 shown in FIG. 10in the prior art for the sake of comparison in case the middle point 43of the switch 39 is connected to the contact 41, i.e., in case theoutput corresponding to the high level period of the pulse train Data isobtained. Here, FIG. 22 shows the case where frequencies and phasescoincide with each other between the pulse train Data and the clocksignal Xck, FIG. 23 shows the case where the clock signal Xck goes aheadof the pulse train Data by 0.25T (where T is one period), FIG. 24 showsthe case where the clock signal Xck lags behind the pulse train Data by0.25T, FIG. 25 shows the case where a frequency f_(xck) of the clocksignal Xck is set higher than the twice of a frequency f_(b) of thepulse train Data (f_(xck)=1.25f_(p)), and FIG. 26 shows the case wherethe frequency f_(xck) of the clock signal Xck is set lower than thefrequency f_(b) of the pulse train Data (f_(xck)=({fraction(1/1.25)})f_(b)=0.8f_(b)). In FIG. 22 to FIG. 26, the delay time of thedelay circuit 15 in the differentiator 3 is 0.6T.

[0161] In FIG. 22 to FIG. 24, it can be understood that encircledportions of the pulse U4 and the pulse D4 as the outputs in theembodiment shown in FIG. 11, i.e., the outputs that correspond to thelow level period of the pulse train Data, can be canceled in the outputpulse U11 and the output pulse D11 in the present embodiment shown inFIG. 21.

[0162] Also, as shown in FIG. 25, it can be understood that, when theclock frequency, i.e., the frequency f_(xck) of the voltage-controlledoscillator 14 is set to the frequency that is 1.25 times the twicefrequency f_(b)(=1/T) of the pulse train Data, the pulse DL1 has theoverwhelmingly wider width than the pulse UL1 in comparison with theoutput pulse UL1 and the output pulse DL1. Since the pulse DL1 is thelagging phase instructing pulse, this wider wide of the lagging phaseinstructing pulse signifies that this pulse acts to lower the clockfrequency f_(xck). In contrast, as shown in FIG. 10, it can beunderstood that the pulses having the almost equal width are outputalternatively as the output pulse UL2 and the output pulse DL2 in theprior art. Strictly speaking, the pulse DL2 (lagging phase instructingpulse) has the slightly wide width, but the frequency and the phase arelocked by this frequency if the current on the pulse UL2 side, i.e., thecharging current is slightly large in the charge pump unit 12 at thesucceeding stage. That is, the fatal defect appears such that the falsepulling is caused. This “1.25 times” shows that the twice frequencyf_(b) of the pulse train Data and the local clock frequency f_(xck) arethe relationship of “f_(xck):f_(b)=5:4”. In the prior art shown in FIG.10, there is the drawback that the false pulling of the frequency iscaused in such integer proportional relationship.

[0163] In this case, it is found that, if the delay time of the delaycircuit 15 is set longer than 0.5T as the ideal delay time, e.g., is setto 0.6T, the possibility of the false pulling can be reduced.

[0164] As shown in FIG. 26, if conversely the clock frequency f_(xck) islow (f_(xck)=({fraction (1/1.25)})f_(b)=0.8f), there is the highpossibility to cause the false pulling in the pulse UL2 and the pulseDL2. This shows the case where the above frequency relationship is“f_(xck):f_(b)=4:5”.

[0165] In this fashion, according to this embodiment, any one of threecases, i.e., the case where the pulse UL1 and the pulse DL1 in which thephase/frequency are compared with each other in both the high levelperiod and the low level period of the pulse train Data are output, thecase where the pulse UL1 and the pulse DL1 in which the phase/frequencythat correspond to only the high level period are compared with eachother are output, and the case where the pulse UL1 and the pulse DL1 inwhich the phase/frequency that correspond to only the low level periodare compared with each other are output, can be selected by switchingthe switch 39. In addition, since the differentiated pulse trainData_Dif, that is the differentiated pulse at the rise and the fall ofthe pulse train Data, and the clock signal Xck as it is are input intothe phase comparator itself, the phase/frequency comparison without theerror can be executed. Also, since comparing chances are increased byexecuting the phase/frequency comparison in both the high level periodand the low level period, quick frequency pulling can be achieved.Accordingly, any one of the high level period and the low level periodis selected by positioning the switch 39 at the position of the contact40 in the frequency pulling stage such as the power supply turning-ONtime and then switching the switch 39 into the contact 41 or the contact42 after the predetermined time has lapsed, and thus the phase comparedoutput containing small jitters can be obtained.

[0166] In the above embodiment, the selection is made by using theswitch 39. But the middle point 43 may be connected to any of thecontacts 40, 41. 42 from the beginning without the provision of theswitch 39.

[0167] <<Further Embodiment>>

[0168] Next, in an embodiment shown in FIG. 27, the method of resettingthe correcting pulse generating portion 18 in the synchronizing signalextracting device 301 shown in FIG. 21 is modified. More particularly,in FIG. 21, the D flip-flop circuit 24 in the correcting pulsegenerating portion 18 is reset by the differentiated pulse trainData_Dif that is input into the input terminal 5. Therefore, in thesynchronizing signal extracting device 301 shown in FIG. 21, sometimesthe false locking phenomenon occurs according to the reset timing of thecorrecting pulse generating portion 18.

[0169] For this reason, in order to overcome the above problem, the Dflip-f lop circuit 24 is reset by an output of a differentiator 51 thatis additionally provided in the correcting pulse generating portion 18.The differentiator 51 differentiates the differentiated pulse trainData_Dif The differentiator 51 consists of a delay circuit 52 and anexclusive-NOR circuit 53, like the differentiator 3. The delay circuit52 delays the output of the delay circuit 15 by a time described later.The exclusive-NOR circuit 53 calculates the exclusive-OR between thediscontinuous pulse train Data input into the input terminal 2 and thedelayed pulse train Data output from the delay circuit 52, thengenerates a reset signal Vreset consisting of the inverted pulses of thepulses In the pulse train Data, that have the width that is equal to thedelay times of the delay circuit 15 and the delay circuit 52, and thensupplies them to the reset terminal of the D flip-flop circuit 24.

[0170] Here, the configuration in FIG. 21 corresponds to the case wherethe delay time of the newly provided delay circuit 52 is 0. In thesynchronizing signal extracting device 301 having such configurationshown in FIG. 21, no problem occurs if the frequency is increased fromthe lower frequency toward the target frequency, nevertheless in somecases the false locking is caused at the frequency higher than thetarget frequency depending upon the delaying way in the delay circuit 15if the frequency is decreased from the higher frequency toward thetarget frequency. This false locking phenomenon will be explained withreference to FIG. 28 hereunder.

[0171]FIG. 28 is a time chart showing the case where the delay time ofthe delay circuit 15 is 0.3T, the delay time of the delay circuit 52 is0, and the local clock frequency f_(xck) is 22.22 MHz. This local clockfrequency f_(xck)=22.22 MHz is the frequency that has the relationshipof f_(xck):f_(b)=10:9 with respect to the bit clock frequency f_(b)=20MHz. In this manner, the false locking occurs at the local frequencythat has the integer ration to the bit clock frequency. In this case,the above frequency having the relationship of f_(xck):f_(b)=5:4 is 25MHz.

[0172] In FIG. 28, since the delay time of the delay circuit 52 is 0,the reset signal Vreset has the same waveform as the differentiatedpulse train Data_Dif output from the differentiator 3. Also, as shown inFIG. 27, since the clock being obtained by Inverting the clock signalXck by the inverter circuit 23 is input into the clock input terminal ofthe D flip-flop circuit 24, such D flip-flop circuit 24 outputs “1” atthe fall of the clock signal Xck.

[0173] In FIG. 28, since the time of the rise b of the reset signalVreset is earlier in time than the fall d of the clock signal Xck, thereset of the D flip-flop circuit 24 is canceled at the time of the falld of the clock signal Xck, and thus the output (pulse E) of the Dflip-flop circuit 24 becomes “1” at the time e.

[0174] When the output (pulse E) of the D flip-flop circuit 24 is “1”,the D flip-flop circuit 21 and the D flip-flop circuit 22 are resetsimultaneously at the time of the rise f of the succeeding clock signalXck. After the D flip-flop circuit 21 and the D flip-flop circuit 22 arereset, one of the D flip-flop circuit 21 and the D flip-flop circuit 22is set to “1” correspondingly at the earlier rise of the differentiatedpulse train Data_Dif and the clock signal Xck.

[0175] In this case, since the time of the rise i of the differentiatedpulse train Data_Dif comes earlier, the output (pulse UL1 a) of the Dflip-flop circuit 21 is set to “1” at the time of the rise j and then isreset at the time of the rise m of the succeeding clock signal Xck. Thatis, the output (pulse UL1 a) of the D flip-flop circuit 21 is kept at“1” in the period j-n, and thereafter the output (pulse UL1 a) of the Dflip-flop circuit 21 outputs “1” in a similar manner. This is the outputto increase the frequency. In this manner, since the output to Increasefurther the frequency is issued although the clock signal Xck is high,not the negative feedback but the positive feedback is executed to causethe oscillation. Also, in the case of 25 MHz, because of the samereason, the pulses having substantially equal and balanced widths aregenerated as the output (pulse UL1 a) of the D flip-flop circuit 21 andthe output (pulse DL1 a) of the D flip-flop circuit 22.

[0176] In order to overcome this problem in the configuration in FIG.21, it may be thought of that the reset state of the D flip-flop circuit24 is extended in time much more. The simplest method is to extend thedelay time of the delay circuit 15, e.g., is set to 0.6T to 0.7T.However, since the delay time of the delay circuit 15 decides the timingserving as the reference of the phase comparison, it is desired that thelead and the lag of the phase should be compared by the equal width.That is, it is desired that the delay time of the delay circuit 15should be set to ½ of the bit width, i.e., 0.5T.

[0177] Therefore, as shown in FIG. 27, the differentiator 51 that isable to control the reset time of the delayed flip-flop circuit 24independently is newly provided, and thus the reset time of the Dflip-flop circuit 24 can be set longer by the delay circuit 52.

[0178] Now, because it may be guessed that the delay times of the delaycircuit 15 and the delay circuit 52 are varied according to fabricationconditions of the delay elements, and operation conditions such as thevoltage, the temperature, etc,, it is desired that the operating marginshould be set as large as possible and that the delay circuit can beoperated perfectly by the about 0.3T as the delay time of the delaycircuit 15. In contrast, it is preferable that the delay time of theadded delay circuit 52 should be set longer. However, if such delay timeis set too longer, the false pulse is generated at the time of normallock, i.e., when both the frequency and the phase coincide with eachother. With the above, it is desired that the delay time of the delaycircuit 52 should be set to less than 0.5T.

[0179] Next, an operation of the configuration shown in FIG. 27 will beexplained with reference to a time chart shown in FIG. 29 hereunder. InFIG. 29, in order to uniformize the conditions, the local clockfrequency f_(xck)=22.22 MHz is employed, the delay time of the delaycircuit 15 is 0.3T, and the delay time of the delay circuit 52 is 0.3T.

[0180] In FIG. 29, since the reset signal Vreset is “0” in the perioda-b and the time of the rise d of the clock signal Xck exists in thisperiod, the D flip-flop circuit 24 is reset continuously, and thus theoutput (pulse E) of the D flip-flop circuit 24 is kept at “0” withoutthe influence of the fall d of the clock signal Xck. Accordingly, the Dflip-flop circuit 22 is set at the time of the rise f of the succeedingclock signal Xck, and the output (pulse DL1 a) normally becomes “1” atthe time g.

[0181] In this fashion, only the output (pulse DL1 a) of the D flip-flopcircuit 22 is generated. That is, the normal output to reduce thefrequency further more is generated, and thus the false lock is nevercaused.

[0182] As the results of various confirmations, it can be found that, ifthe delay time of the delay circuit 52 is 0.3T, no false lock is causeduntil the delay time of the delay circuit 15 is 0.3 T to 0.6T and, ifthe delay time of the delay circuit 52 is 0.4T, no false lock is causeduntil the delay time of the delay circuit 15 is 0.2 T to 0.5T.

[0183] <<Still Further Embodiment>>

[0184]FIG. 31 is a time chart showing the case where the clock signalXck leads in phase 0.2T than the differentiated pulse train Data_Dif inthe synchronizing signal extracting device shown in FIG. 27. In thiscase, no false pulse appears in the signal of pulse DL1. However, if thedelay time of the delay circuit 15 is set so large that the clock signalXck leads in phase 0.5T than the differentiated pulse train Data_Dif.false pulses Pa, Pb and Pc appear in the signal of pulse DL1 as shown inFIG. 32. Also, when the frequency of the clock signal Xck is higher thanthe differentiated pulse train Data_Dif, false pulses appear in thesignal of pulse DL1 as shown in FIGS. 33 and 34.

[0185] In order to overcome the above drawback, according to thisembodiment, the correcting pulse generating portion 18 in thesynchronizing signal extracting device shown in FIG. 27 is modified.

[0186]FIG. 30 is a circuit diagram showing a synchronizing signalextracting device including the modified correcting pulse generatingportion 54. In addition to the differentiator 51, the inverter circuit23 and the D flip-flop circuit 24, the modified correcting pulsegenerating portion 54 includes an inverter circuit 55, a D flip-flopcircuit 56 and an OR circuit 57.

[0187] The inverter circuit 55 Is a circuit for inverting a clock signalXck2 being output from the voltage-controlled oscillator 14 and inputinto the input terminal 58. The D flip-flop circuit 56 acquires the “1”signal being input into the data Input terminal D every time when theinverted clock signal Xck2 output from the inverter circuit 55 israised. and outputs this signal from the data output terminal Q whileholding this, and also resets the held content to then output the “0”signal from the data output terminal Q every time when the reset signalVreset output from the differentiator 51 is “1” and thus the “0” signal(the “1” signal in the negative logic) is input into the reset terminalR. The OR circuit 57 calculates the logical sum of the pulse E outputfrom the data output terminal Q of the D flip-flop circuit 24 and thepulse E1 output from the data output terminal Q of the D flip-flopcircuit 56.

[0188]FIG. 35 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 30. The clock signal Xck2 beingoutput from the voltage-controlled oscillator 14 lags behind the clocksignal Xck1 by 90 degrees as shown in FIG. 35. The clock signal Xck2 maybe easily generated such that the voltage-controlled oscillator 14 ismaterialized as an oscillator constructed by including even number stageconnection of differential amplifiers and cross connection of inputstage thereof and a signal of the intermediate point of the oscillatoris picked up. Therefore, a signal such as the clock signal Xck2 has beenpopularly used in a quadricorrelator and so on.

[0189] As already described above, the D flip-flop circuit 56 istriggered by the clock signal Xck2 that lags behind the clock signalXck1 by 90 degrees. Thus, not only the pulse E output from the Dflip-flop circuit 24 triggered by the clock signal Xck1 but also thepulse E1 output from the D flip-flop circuit 56 triggered by the clocksignal Xck2 are used as a correcting pulse for the pulse correctingportion 20. With this configuration, no false pulse appears in thesignal of pulse DL1 even when the clock signal Xck1 leads in phase 0.5Tthan the differentiated pulse train Data_Dif. Further, no false pulseappears in the signal of pulse DL1 also even when the frequency of theclock signal Xck1 is higher than that of the differentiated pulse trainData_Dif as shown in FIGS. 36 and 37 corresponding to FIGS. 33 and 34,respectively.

[0190] Accordingly, it becomes possible to reproduce stable clock anddata even when the delay times of the delay circuits 15 and 52 vary dueto temperature, voltage, manufacturing condition and so on.

[0191] <<Yet Still Further Embodiment>>

[0192] On the other hand, under a certain condition, the configurationof the synchronizing signal extracting device shown in FIG. 27 can besimplified.

[0193]FIG. 38 is a circuit diagram showing a synchronizing signalextracting device including the modified correcting pulse generatingportion 59. The modified correcting pulse generating portion 59 isconstructed such that the inverter circuit 23 and the D flip-flopcircuit 24 are deleted from the correcting pulse generating circuit 18.That is, the modified correcting pulse generating portion 59 includesonly the delay circuit 52 and the exclusive-NOR circuit 53, Thus, theoutput signal of the exclusive-NOR circuit 53, i.e., reset signalVreset, is directly used for the resetting portion 19 and the pulsecorrecting portion 20.

[0194]FIG. 39 is a time chart showing an operation of the synchronizingsignal extracting device shown in FIG. 38.

[0195] Even such a device having such above configuration would functionproperly as shown in FIG. 39, when the clock signal Xck leads in phase0.5T than the differentiated pulse train Data_Dif. The reason is that,if the sum of the delay times of the delay circuits 15 and 16substantially coincides with bit width T, the reset signal Vresetobtained by performing exclusive-NOR operation on a signal delayed bythe delay circuits 15 and 16 and the pulse train Data presents “0” or“1” depending on whether the pulse train Data is in pulse missing stateor not so that the reset signal Vreset can be directly used as a signalfor the pulse correcting portion 20.

[0196] The cases shown in FIGS. 40 and 41, in which the frequency of theclock signal Xck is higher than that of the differentiated pulse trainData_Dif, also function properly just the same as the cases shown inFIGS. 36 and 37.

[0197] However, it should be noted that the device shown in FIG. 38 doesnot operate expectedly under a certain frequency relation of the clocksignal Xck and the differentiated pulse train Data_Dif and a certaindelay time of the delay circuit 52, as described hereunder.

[0198] Generally, there is a possibility of false pulling of frequencyand freezing in the pulling frequency or oscillation at the stage offrequency pulling in the following relation of the frequency fxck of theclock signal Xck and the frequency fb of the pulse train Data.

fxck=((2n+1)/2n)fb

or fxck=((2n−1)/2n)fb

[0199] where n is a given integer.

[0200] Particularly, when n=4, i.e. fxck=(9/8)fb, it has beenexperientially found that there is a highest possibility of the falsepulling of frequency or the oscillation.

[0201] As already explained, when fxck=(9/8)fb and the delay time of thedelay circuit 52 is 0.4T as shown in FIG. 41, proper pulses fordecreasing the frequency are generated without any problem. However,when the delay time of the delay circuit 52 is 0.6T under the samefrequency condition as shown in FIG. 42, false pulses are generated inthe signal UL1 after time t1 or t2, though corresponding pulses shouldbe generated in the signal DL1. This is because a rising of the clocksignal Xck at the time t1 or t2 occurs during the reset signal Vreset isin the high level (“1”) thereof, therefore, both the D flip-flop circuit21 and the D flip-flop circuit 22 are reset at the time t1 or t2 so thata rising of the differentiated pulse train Data_Dif which appearsearlier than the next rising of the clock signal Xck causes the Dflip-flop circuit 21 to be set to “1”.

[0202] In view of the above, it is necessary that the delay time of thedelay circuit 52 is equal to or less than 0.4T in the embodiment shownin FIG. 38. In this connection, an ideal condition for detecting anincomplete pulse signal having some missing pulses is that the delaytime of the delay circuit 15 is 0.6T and the delay time of the delaycircuit 52 is 0.4T (0.6T+0.4T=1T), and under this condition, the resetsignal Vreset shows “1” for a duration accurately corresponding to aduration in which pulses are missing and shows “0” for the otherduration. Incidentally, at the present time, it is impossible toforecast whether the next pulse to be is missing. Therefore, past datathat precedes by one bit is stored in a delay circuit and then presentdata is compared with the past data so that it may be possible todetermine whether the present data corresponds to data of a missingpulse. In this sense, the delay circuit is an important storage element.

[0203] Different from the device shown in FIG. 38, the both devicesshown in FIGS. 27 and 30 properly operate even in the condition shown inFIG. 42, because the pulse E triggered by a falling edge of the clocksignal Xck(Xck1) that appears after a rising edge of the clock signalXck(Xck1) is used as a correcting pulse in the device shown in FIG. 27and the pulse E1 triggered by a falling edge of the clock signal Xck2 isadditionally used as a correcting pulse in the device shown In FIG. 30so that a rising of the clock signal Xck(Xck1) never occurs during thepulse E or E1 is in the high level (“1”) during pulse missing state.Although the rising occurs during the pulse E or E1 is in the high level(“1”) during normal state, there is no problem since the comparisonoperation is inhibited by resetting both the D flip-flop circuit 21 andthe D flip-flop circuit 22.

[0204] Meanwhile, with regard to frequency pulling-in, according to theabove two embodiments, even under the condition where the frequencyfxck1(fxck) of the clock signal Xck1(xck) is considerably higher than,for example, twice as high as that of the differentiated pulse trainData_Dif as shown in FIGS. 36 and 40, the wide pulse DL1 for stronglydecreasing the frequency of the clock signal is generated.

[0205] On the other hand, under the condition where the frequencyfxck1(fxck) of the clock signal Xck1(xck) is considerably lower than,for example, half of that of the differentiated pulse train Data_Dif,the wide pulse UL1 for strongly increasing the frequency of the clocksignal is generated according to the embodiments, though not shown inthe drawings.

[0206] Other frequency discriminating means such as a quadricorrelatorand a rotational slip detector do not have the above feature. That is,according to these frequency discriminating means, although a strongpulling signal is generated when the frequency of the clock signal isnear the frequency of the pulse train of original data, the pullingsignal becomes week as the frequencies depart from each other andresulting in that no pulling signal appears when the frequency of theclock signal is twice or half.

[0207] In contrast, according to the embodiments, there is no demeritsuch as above and a strong pulling signal is generated depending on onlywhether the frequency is higher or lower and not depending on the degreethereof. Further, once the frequencies coincide with each other and thena phase-pulling stage comes, a strong phase-pulling signal is generatedsimilarly. Furthermore, the frequency-pulling stage is continuously andsmoothly followed by the phase-pulling stage without any pause. Inaddition, the devices according to the embodiments have a characteristicof an almost ideal frequency/phase comparator such that only an outputsignal including pulses having width of nearly zero is generated at apoint of coincidence in frequency and phase.

[0208] In conclusion, from the foregoing descriptions, it is found thatthe device shown in FIG. 38 is preferable when a stable delay circuit isavailable, and the device shown in FIG. 27 is preferable in practicaluse, and the device shown in FIG. 30 is preferable when it is necessaryto keep an operation margin enough.

[0209] As described above, according to the present invention, theprecise synchronizing signal can be generated with respect to the pulsetrain that is brought into the tooth missing state due to a modulationby data, while reducing the number of parts. Also, the pulsation of thedetected output can be minimized as small as possible to zero at thepoint of time when the synchronizing signal having the matched frequencyand phase is obtained, and the variable range of the detected output canbe expanded. As a result, the frequency variable range of thesynchronizing signal can be expanded to enable the high speed response,and also the frequency discriminating function can be provided.

[0210] It should be understood that many modifications and adaptationsof the invention will become apparent to those skilled in the art and itis Intended to encompass such obvious modifications and changes in thescope of the claims appended, hereto.

What is claimed is:
 1. A phase comparator (9:41) comprising: a phasecomparing portion (17) for generating a leading phase instructing pulse(U4) and a lagging phase instructing pulse (D4 a) to mate a phase of aninput pulse train (Data_Dif) and a phase of an input clock signal (Xck1)with each other in accordance with the phases; a correction pulsegenerating portion (18) for generating a correction pulse (E:E1) inaccordance with the input pulse train and the input clock signal; and aresetting portion (19:40) for resetting the phase comparing portion (17)by generating a reset pulse in accordance with the leading phaseinstructing pulse and the lagging phase instructing pulse output fromthe phase comparing portion (17), the correction pulse (E:E1) outputfrom the correction pulse generating portion (18), and the input clocksignal.
 2. A phase comparator (9:41) comprising: a phase comparingportion (17) for generating a leading phase instructing pulse (U4) and alagging phase instructing pulse (D4 a) to mate a phase of an input pulsetrain (Data_Dif) and a phase of an input clock signal (Xck1) with eachother in accordance with the phases; a correction pulse generatingportion (18) for generating a correction pulse (E:E1) in accordance withthe input pulse train and the Input clock signal; a resetting portion(19:40) for resetting the phase comparing portion (17) by generating areset pulse in accordance with the leading phase instructing pulse andthe lagging phase instructing pulse output from the phase comparingportion (17), the correction pulse (E:E1) output from the correctionpulse generating portion (18), and the input clock signal: and a pulsecorrecting portion (20) for removing false pulses contained in thelagging phase instructing pulse (D4 a) output from the phase comparingportion (17), based on the correction pulse (E:E1) output from thecorrection pulse generating portion (18).
 3. A phase comparator (9:41)according to claim 1 , wherein the correction pulse generating portion(18) generates the correction pulse (E) that has a pulse widthequivalent to a time period from a time at which the correction pulse istriggered by the clock signal to a time at which the correction pulse isreset by a differentiated pulse train obtained by differentiating thepulse train, and detects a pulse missing of the input pulse train basedon the pulse width of the correction pulse (E).
 4. A phase comparator(9:41) according to claim 1 . wherein the correction pulse generatingportion (18) generates the correction pulse (E:E1) that has a pulsewidth equivalent to a time period obtained by overlapping a time periodfrom a time at which the correction pulse is triggered by the clocksignal to a time at which the correction pulse is reset by adifferentiated pulse train obtained by differentiating the pulse trainand a time period from a time at which the correction pulse is triggeredby a second clock signal that lags behind the clock signal by apredetermined degrees to a time at which the correction pulse is resetby a differentiated pulse train obtained by differentiating the pulsetrain, and detects a pulse missing of the input pulse train based on thepulse width of the correction pulse (E:E1).
 5. A phase comparator (9)according to claim 1 , wherein the phase comparing portion (17) includesa first flip-flop circuit (21) triggered by a differentiated pulse trainobtained by differentiating the pulse train to output the leading phaseinstructing pulse and a second flip-flop circuit (22) triggered by theclock signal to output the lagging phase instructing pulse, and theresetting portion (19) generates a reset pulse when both the leadingphase instructing pulse and the lagging phase instructing pulse areoutput from the phase comparing portion or when the clock signal isinput in a situation that the correction pulse is being output from thecorrection pulse generating portion, and resets the leading phaseinstructing pulse and the lagging phase instructing pulse by resettingthe respective flip-flop circuits constituting the phase comparingportion.
 6. A phase comparator (41) according to claim 1 , wherein thephase comparing portion (17) includes a first flip-flop circuit (21)triggered by a differentiated pulse train obtained by differentiatingthe pulse train to output the leading phase instructing pulse and asecond flip-flop circuit (22) triggered by the clock signal to outputthe lagging phase instructing pulse, and the resetting portion (40)generates a reset pulse when both the leading phase instructing pulseand the lagging phase instructing pulse are output from the phasecomparing portion, and resets the leading phase instructing pulse andthe lagging phase instructing pulse by resetting the respectiveflip-flop circuits constituting the phase comparing portion; orgenerates a reset pulse when the clock signal is input in a situationthat the correction pulse is being output from the correction pulsegenerating portion and resets the lagging phase instructing pulse byresetting the second flip-flop circuit constituting the phase comparingportion.
 7. A phase comparator according to claim 1 , wherein the phasecomparing portion (17) generates the leading phase instructing pulse andthe lagging phase instructing pulse by using a differentiated pulsetrain obtained by differentiating both of a rise and a fall of the pulsetrain, and selects and outputs portions that correspond to at least oneof a high level period and a low level period of the pulse train fromthe leading phase instructing pulse and the lagging phase instructingpulse.
 8. A phase comparator according to claim 2 , wherein the phasecomparing portion (17) generates the leading phase instructing pulse andthe lagging phase instructing pulse by using a differentiated pulsetrain obtained by differentiating both of a rise and a fall of the pulsetrain, and selects and outputs portions that correspond to at least oneof a high level period and a low level period of the pulse train fromthe leading phase instructing pulse and the lagging phase instructingpulse.
 9. A phase comparator according to claim 3 , wherein the phasecomparing portion (17) generates the leading phase instructing pulse andthe lagging phase instructing pulse by using a differentiated pulsetrain obtained by differentiating both of a rise and a fall of the pulsetrain, and selects and outputs portions that correspond to at least oneof a high level period and a low level period of the pulse train fromthe leading phase instructing pulse and the lagging phase instructingpulse.
 10. A phase comparator according to claim 4 , wherein the phasecomparing portion (17) generates the leading phase instructing pulse andthe lagging phase instructing pulse by using a differentiated pulsetrain obtained by differentiating both of a rise and a fall of the pulsetrain, and selects and outputs portions that correspond to at least oneof a high level period and a low level period of the pulse train fromthe leading phase instructing pulse and the lagging phase instructingpulse.
 11. A phase comparator according to claim 5 , wherein the phasecomparing portion (17) generates the leading phase instructing pulse andthe lagging phase instructing pulse by using a differentiated pulsetrain obtained by differentiating both of a rise and a fall of the pulsetrain, and selects and outputs portions that correspond to at least oneof a high level period and a low level period of the pulse train fromthe leading phase instructing pulse and the lagging phase instructingpulse.
 12. A phase comparator according to claim 6 , wherein the phasecomparing portion (17) generates the leading phase instructing pulse andthe lagging phase instructing pulse by using a differentiated pulsetrain obtained by differentiating both of a rise and a fall of the pulsetrain, and selects and outputs portions that correspond to at least oneof a high level period and a low level period of the pulse train fromthe leading phase instructing pulse and the lagging phase instructingpulse.
 13. A synchronizing signal extracting device (1:301) comprising:a phase comparator (9:41) set forth in claim 1 ; a differentiator (3)for differentiating an pulse train (Data) having a frequency that is ½of a frequency of the input pulse train (Data_Dif), and supplying to thephase comparator as the input pulse train; a charge pump unit (12) forincreasing a voltage value of an output voltage signal by executing acharging operation when the leading phase instructing pulse is inputfrom the phase comparator, and decreasing the voltage value of theoutput voltage signal by executing a discharging operation when thelagging phase instructing pulse is input from the phase comparator; anda voltage-controlled oscillator (14) for receiving the voltage signaloutput from the charge pump unit (12), generating a clock signal havinga frequency that increases as the voltage value of the voltage signalincreases, and supplying the generated clock signal to the phasecomparator (9:41).
 14. A synchronizing signal extracting device (1:301)comprising; a phase comparator (9:41) set forth in claim 2 ; adifferentiator (3) for differentiating an pulse train (Data) having afrequency that is ½ of a frequency of the input pulse train (Data_Dif),and supplying to the phase comparator as the input pulse train; a chargepump unit (12) for increasing a voltage value of an output voltagesignal by executing a charging operation when the leading phaseinstructing pulse Is input from the phase comparator, and decreasing thevoltage value of the output voltage signal by executing a dischargingoperation when the lagging phase instructing pulse is input from thephase comparator; and a voltage-controlled oscillator (14) for receivingthe voltage signal output from the charge pump unit (12). generating aclock signal having a frequency that increases as the voltage value ofthe voltage signal increases, and supplying the generated clock signalto the phase comparator (9:41).